;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE Tanex Plus Paged EPROM GAL U3 PATTERN REVISION V1.0a (For use with Tanex Plus v1.0a) AUTHOR David Fry COMPANY DATE 20/07/16 CHIP TPLUS_U3 PALCE16V8 ;---------------------------------- PIN Declarations --------------- PIN 1 NC ; Spare not used PIN 2 ROM_SEL ; Input ROM bank selection PIN 3 A8 ; Input A8 from address bus PIN 4 A9 ; Input A9 from address bus PIN 5 A12 ; Input A12 from address bus PIN 6 A13 ; Input A13 from address bus PIN 7 A14 ; Input A14 from address bus PIN 8 A15 ; Input A15 from address bus PIN 9 IOW ; Input from U7 IO Write (Active low) PIN 11 MSB9 ; Input DipSW A9 address mask PIN 12 NC ; Pin not avail for input in complex mode PIN 13 MSB8 ; Input DipSW A8 address mask PIN 14 UP_RAM ; Input Switch out EPROM for SRAM (Active High) PIN 15 LSB ; Input from 74LS682 (Active low) PIN 16 PLE ; Output Port Latch Enable (Pos edge) PIN 17 EPR_EN ; Output Eprom Enable (Active low) PIN 18 EPR1 ; Output Eprom 1 Chip Select (Active low) PIN 19 EPR0 ; Output Eprom 0 Chip Select (Active low) ;----------------------------------- Boolean Equation Segment ------ EQUATIONS PLE = /IOW * /LSB * /A9 * /A8 * /MSB9 * /MSB8 + /IOW * /LSB * /A9 * A8 * /MSB9 * MSB8 + /IOW * /LSB * A9 * /A8 * MSB9 * /MSB8 + /IOW * /LSB * A9 * A8 * MSB9 * MSB8 /EPR_EN = /UP_RAM * A15 * A14 * /A13 * /A12 + /UP_RAM * A15 * A14 * /A13 * A12 + /UP_RAM * A15 * A14 * A13 * /A12 EPR0 = ROM_SEL + EPR_EN EPR1 = /ROM_SEL + EPR_EN ;----------------------------------- Simulation Segment ------------ SIMULATION TRACE_ON EPR_EN UP_RAM A15 A14 A13 A12 ;Check valid conditions for EPR0 SETF /UP_RAM A15 A14 /A13 /A12 /ROM_SEL CHECK /EPR0 ;Check valid conditions for EPR1 SETF /UP_RAM A15 A14 /A13 /A12 ROM_SEL CHECK /EPR1 TRACE_OFF ;-------------------------------------------------------------------